In microelectronics, a three dimensional (3D) integrated circuit is manufactured by stacking silicon wafers and/or dies and interconnecting them vertically so that they behave as a single device to achieve performance improvements at reduced power and smaller footprint than conventional two dimensional structures. The manufacture of 3D integrated circuits involves bonding and thinning of top and intermediate wafers; however, wafer-wafer bonding is a challenge and the industry is rigorously working to find efficient, reliable bonding solutions.
Although significant advancements have been made in wafer-wafer bonding technology, bonding at the wafer edge is still a concern. And, as the wafer size increases from 300 mm to 450 mm, bonding at the wafer edge becomes an even bigger problem.
Wafer-wafer bonding requires edge trimming processes. Edge trimming the weak edge bonded regions removes the weakly bonded region and avoids particle contamination in downside processing. Edge trimming requires trimming only the top wafer of the bonded pair however, stopping the trim process exactly at the bonding interface is a challenge due to many factors. These factors include, e.g., low tolerance of the existing edge trim tool which is approximately +/−15-20 μm; shallow edge trim leaves the top wafer and can cause foreign material (FM) and deeper edge trim can result in the bottom wafer being thinned too much and hence having greater chances of chipping or breaking.